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BSI
n FEATURES
Ultra Low Power/High Speed CMOS SRAM 256K X 16 bit
Y Y Y Y
BS616UV4016
Y Wide VCC operation voltage : C-grade : 1.8V ~ 3.6V I-grade : 1.9V ~ 3.6V (VCC_min.=1.65V at 25OC) Y Ultra low power consumption : VCC = 2.0V C-grade : 10mA(Max.) operating current I-grade : 12mA(Max.) operating current 0.3uA (Typ.) CMOS standby current VCC = 3.0V C-grade : 13mA(Max.) operating current I-grade : 15mA(Max.) operating current 0.45uA (Typ.) CMOS standby current Y High speed access time : -85 85ns (Max.) -10 100ns (Max.) Y Automatic power down when chip is deselected Y Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin. Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 1.2V
n DESCRIPTION
The BS616UV4016 is a high performance, ultra low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates form a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.3uA at 2.0V/25OC and maximum access time of 85ns at 85OC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616UV4016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV4016 is available in DICE form, JEDEC standard 44-pin TSOP Type II and 48-ball BGA package.
n PRODUCT FAMILY
PRODUCT FAMILY
BS616UV4016DC BS616UV4016EC BS616UV4016AC BS616UV4016DI BS616UV4016EI BS616UV4016AI -40OC to +85OC 1.9V ~ 3.6V 85/100 8.0uA 5.0uA 15mA 12mA +0 C to +70 C
O O
OPERATING TEMPERATURE
VCC RANGE
SPEED (ns)
C-grade : 1.8~3.6V I-grade : 1.9~3.6V
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V
DICE 1.8V ~ 3.6V 85/100 6.0uA 3.0uA 13mA 10mA TSOP2-44 BGA-48-0608 DICE TSOP2-44 BGA-48-0608
n PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC GND IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB IO15 IO14 IO13 IO12 GND VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12
n BLOCK DIAGRAM
BS616UV4016EC BS616UV4016EI
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Address Input Buffer
10 Row Decoder
1024
Memory Array
1024 x 4096
2048 IO0 . . . . . . IO15 . . . . . . 16 Data Input Buffer Data Output Buffer 16 256 Column Decoder 8 Control Address Input Buffer 16 Column I/O Write Driver Sense Amp
1 A B C D E F G H UB IO8 IO9 VSS VCC IO14 IO15 NC
2 OE LB IO10 IO11 IO12 IO13 NC A8
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE IO1 IO3 IO4 IO5 WE A11
6 NC IO0 IO2 VCC VSS IO6 IO7 NC
16
CE WE OE UB LB VCC GND
A13 A14 A15 A16 A17 A0 A1 A2
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616UV4016
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Revision 1.3 Sep. 2005
BSI
n PIN DESCRIPTIONS
BS616UV4016
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM
Name
A0-A17 Address Input CE Chip Enable 1 Input
CE is active LOW. Chip enable must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The IO pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the IO pins; when WE is LOW, the data present on the IO pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the IO pins and they will be enabled. The IO pins will be in the high impendence state when OE is inactive. Lower byte and upper byte data input/output control pins.
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input IO0-IO15 Data Input/Output Ports VCC GND
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n TRUTH TABLE MODE
Chip De-selected (Power Down)
CE
H X L
WE
X X H H
OE
X X H H
LB
X H L X L
UB
X H X L L L H L L H
IO0~IO7
High Z High Z High Z High Z DOUT High Z DOUT DIN X DIN
IO8~IO15
High Z High Z High Z High Z DOUT DOUT High Z DIN DIN X
VCC CURRENT
ICCSB, ICCSB1 ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC ICC
Output Disabled L
Read
L
H
L
H L L
Write
L
L
X
H L
NOTES: H means VIH; L means VIL; X means don't care (Must be VIH or VIL state)
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Revision 1.3 Sep. 2005
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n ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG PT IOUT
(1)
BS616UV4016
n OPERATING RANGE
UNITS
V
O O
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
-0.5
(2)
RANG
Commercial Industrial
AMBIENT TEMPERATURE
0 C to + 70 C -40OC to + 85OC
O O
Vcc
1.8V ~ 3.6V 1.9V ~ 3.6V
to 4.6V
-40 to +85 -60 to +150 1.0 20
C C
W MA
n CAPACITANCE
(1)
(TA = 25 C, f = 1.0MHz)
O
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF
1. This parameter is guaranteed and not 100% tested.
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC ICCSB ICCSB1
(5)
O
O
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
1.9
VCC=2.0V VCC=3.0V
TYP.(1)
--
MAX.
3.6 0.6 0.8
UNITS
V
Input Low Voltage
-0.3(2) 1.4 2.0 --
--
V
Input High Voltage VIN = 0V to VCC, CE = VIH VI/O = 0V to V CC CE= VIH, or OE = VIH V CC = Max, IOL = 0.1mA V CC = Max, IOL = 2.0mA Output High Voltage Operating Current Power Supply V CC = Min, IOH = -0.1mA V CC = Min, IOH = -1.0mA CE = VIL, IIO = 0mA, f = FMAX(4) CE = VIH, IIO = 0mA CEVCC-0.2V, VINV CC-0.2V or VIN0.2V
VCC=2.0V VCC=3.0V
--
VCC+0.3(3)
V
Input Leakage Current
--
1
uA
Output Leakage Current
-VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V VCC=3.0V
--
1 0.2 0.4
uA
Output Low Voltage
-VCC-0.2 2.4 --
--
V
--
-12 15
V
--
mA
Standby Current - TTL
--
-0.3 0.45
0.5 1.0
mA
Standby Current - CMOS
--
5.0 8.0
uA
1. Typical characteristics are at TA=25OC. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICCSB1(MAX) is 3.0/6.0uA at VCC=2.0V/3.0V and TA=70OC.
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Revision 1.3 Sep. 2005
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n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
SYMBOL VDR ICCDR
(3)
BS616UV4016
O O
PARAMETER
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
TEST CONDITIONS
CEVCC-0.2V, VINV CC-0.2V or VIN0.2V CEVCC-0.2V, VINV CC-0.2V or VIN0.2V
MIN.
1.2 -0
TYP. (1)
-0.15 ---
MAX.
-1.7 ---
UNITS
V uA ns ns
tCDR tR
See Retention Waveform tRC (2)
1. VCC=1.2V, TA=25 C. 2. tRC = Read Cycle Time. 3. ICCRD_Max. is 1.2uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode VDR1.0V
VCC
VIH
VCC
VCC
tCDR
CEVCC - 0.2V
tR
VIH
CE
n AC TEST CONDITIONS
(Test Load and Input/Output Reference) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND
10% 90% 90% 10%
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM "H" TO "L" MAY CHANGE FROM "L" TO "H" DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM "H" TO "L" WILL BE CHANGE FROM "L" TO "H" CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE "OFF" STATE
Rise Time: 1V/ns
Fall Time: 1V/ns
1. Including jig and scope capacitance.
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n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Data Byte Control to Output High Z Output Enable to Output High Z Data Hold from Address Change (CE) (LB, UB) (CE) (LB, UB) (CE) (LB, UB) CYCLE TIME : 85ns (VCC=1.9~3.6V) MIN. TYP. MAX. 85 ----15 15 15 ---15 -------------85 85 40 40 ---35 35 35 -O O
BS616UV4016
CYCLE TIME : 100ns (VCC=1.9~3.6V) MIN. TYP. MAX. 100 ----15 15 15 ---15 -------------100 100 50 50 ---40 40 40 --
UNITS ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQX tELQV tBLQV tGLQV tELQX tBLQX tGLQX tEHQZ tBHQZ tGHQZ tAVQX
tRC tAA tACS
(1) tBA
tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
NOTE : 1. tBA is 40ns/50ns(@speed=85ns/100ns) with address toggle; tBA is 85ns/100ns(@speed=85ns/100ns) without address toggle
n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1
(1,2,4)
tRC ADDRESS tOH DOUT tAA tOH
READ CYCLE 2 CE
(1,3,4)
tACS tBA LB, UB tBE DOUT tCLZ
(5)
tCHZ tBDO
(5)
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Revision 1.3 Sep. 2005
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READ CYCLE 3
(1, 4)
BS616UV4016
tRC
ADDRESS tAA OE tOE CE tCLZ LB, UB
(5)
tOH
tOLZ tACS tBA tBE tBDO tOHZ tCHZ
(5)
(1,5)
DOUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.
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Revision 1.3 Sep. 2005
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n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Address Set up Time Address Valid to End of Write Chip Select to End of Write Data Byte Control to End of Write Write Pulse Width Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE, WE) (CE) (LB, UB) CYCLE TIME : 85ns (VCC=1.9~3.6V) MIN. TYP. MAX. 85 0 85 85 35 40 0 -35 0 -10 -------------------35 --35 -O O
BS616UV4016
CYCLE TIME : 100ns (VCC=1.9~3.6V) MIN. TYP. MAX. 100 0 100 100 40 50 0 -40 0 -10 -------------------40 --40 -UNITS ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAS tAW tCW
(1) tBW
tWP tWR tWHZ tDW tDH tOHZ tOW
NOTE: 1. tBW is 35ns/40ns (@speed=85ns/100ns) with address toggle; tBW is 85ns/100ns (@speed=85ns/100ns) without address toggle.
n SWITCHING WAVEFORMS (WRITE CYCLE) (1) WRITE CYCLE 1
tWC ADDRESS
OE tCW CE
(5) (11)
tBW LB, UB tAW WE tAS tOHZ DOUT tDH tDW DIN
(4,10) (3)
tWR tWP
(2)
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Revision 1.3 Sep. 2005
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WRITE CYCLE 2
(1,6)
BS616UV4016
tWC
ADDRESS tCW
(11)
CE
(5)
tBW LB, UB tAW WE tAS tWHZ DOUT tDW tDH DIN
(8,9) (4,10) (3)
tWP
(2)
tWR
tOW
(7)
(8)
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, IO pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, IO pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write.
R0201-BS616UV4016
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Revision 1.3 Sep. 2005
BSI
n ORDERING INFORMATION
BS616UV4016
X X Z YY
SPEED 85: 85ns 10: 100ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C : +0oC ~ +70oC I : -40oC ~ +85oC
BS616UV4016
PACKAGE D: DICE E: TSOP 2-44 A: BGA-48-0608
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616UV4016
E1
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Revision 1.3 Sep. 2005
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n PACKAGE DIMENSIONS (continued)
BS616UV4016
TSOP2-44
R0201-BS616UV4016
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Revision 1.3 Sep. 2005

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